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Wei Chen Location
Saratoga, CA, US
Wei Chen Work
Senior Design Manager @ (July 2021 - Present)
Principal Design Engineer @ (March 2005 - July 2021)
Design Engineer @ Intersil (January 2005 - January 2011)
Wei Chen Education
The Hong Kong University of Science and Technology
Master (EE)
1998-2001
Zhejiang University
Bachelor (EEE)
1994-1998
Wei Chen Skills
Analog
Analog Circuit Design
Cadence
Circuit Design
IC
Integrated Circuit Design
Integrated Circuits (IC)
Power Electronics
Power Management
SPICE
Semiconductors
VLSI
Integrated Circuits Ic
Integrated Circuits
Wei Chen Summary
Wei Chen, based in Saratoga, CA, US, is currently a Senior Design Manager at Intersil (acquired by Renesas). Wei Chen brings experience from previous roles at Intersil (acquired by Renesas) and Intersil. Wei Chen holds a 1998 - 2001 Master in EE @ The Hong Kong University of Science and Technology. With a robust skill set that includes Analog, Analog Circuit Design, Cadence, Circuit Design, IC and more. Wei Chen has 1 emails and 4 mobile phone numbers on RocketReach.
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