Henry Yao Email & Phone Number
ASIC Design Manager @ Intersil (acquired by Renesas)
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Henry Yao Location
- San Jose, CA, US
Henry Yao Work
- 2010 -now ASIC Design Manager @
- 2005 -2010 Sr. ASIC Design Engineer @
- 2002 -2005 ASIC Design Manager @ ViChip Corp.
- 2001 -2002 Sr. Design Engineer @
- 1998 -2000 Sr. Design Engineer. @ RapidStream Inc.
- 1996 -1998 Sr. ASIC Design Engineer. @ NPL Labs.
- 1994 -1996 Sr. Design Engineer. @ S3 Inc.
Henry Yao Education
- University of Southern California
Master of Science (MS) (EECS)
1985-1987 - National Taiwan University
Bachelor of Science (BS) (EECS)
1979-1982
Henry Yao Skills
- Strategic Planning
- Video Codec
- Integration and Validation
- Logic Synthesis
- Internet Security
- Engineering
- Wireless Phy
- Fast Ethernet
- FPGA
- Surveillance
- IC
- Video Image/Stream
- ASIC
- Graphic Design
- Dsp Hardware Accelerator
- Digital/Mix Mode Asic
- CMOS
- VLSI
- Java
- Semiconductors
- Digital Signal Processors
- Video Surveillance
- Video Image/Stream Processing
- InDesign
- Digital Signal
- Mixed Signal
- SoC
- SPI
- Static Timing Analysis
- Digital/Mix Mode Asic Design
- Embedded Systems
- PCIe
Henry Yao Summary
- Henry Yao, based in San Jose, CA, US, is currently a ASIC Design Manager at Intersil. Henry Yao brings experience from previous roles at Techwell, ViChip Corp., VIA Technologies, Inc. and RapidStream Inc.. Henry Yao holds a 1985 - 1987 Master of Science (MS) in EECS @ University of Southern California. With a robust skill set that includes Strategic Planning, Video Codec, Integration and Validation, Logic Synthesis, Internet Security and more. Henry Yao has 1 emails and 2 mobile phone numbers on RocketReach.
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