Wade Wang Email & Phone Number
System Design Architect (Cadence SSG System, Chiplet IP, NoC, NPU, DSP) @ Cadence Design Systems
Wade Wang Location
San Jose, CA, US
Wade Wang Work
- 2016 - now System Design Architect (Cadence SSG System, Chiplet IP, NoC, NPU, DSP) @ Cadence Design Systems
- 2021 - 2021 SoC ASIC Architect (Principal Engineer) @ Tencent US
- 2007 - 2015 Camera ISP System ASIC Hardware Architect @ Qualcomm
- 2007 - 2015 Camera ISP System ASIC Hardware Architect (Cont'd) @ Qualcomm
- 2007 - 2015 Graphics (GPU) ASIC RTL Emulation Lead @ Qualcomm
- 2005 - 2007 Sr. ASIC Engineer @ AMD (merged from ATI)
- 2003 - 2005 Embedded System Hardware Architect @ Microsym Computers (sold)
- 2000 - 2002 ASIC and FPGA RTL Designer @ Nortel Networks, Hatteras Networks
Wade Wang Education
- University of New Brunswick
Master's Degree (Very-Large-Scale Integration (VLSI) in Dept of ECE)
1997 - 2000 - Huazhong University of Science and Technology
Ph.D Candidate (Precision Instruments)
1994 - 1996 - Wuhan University
Master's Degree (Computer Engineering, BSEE in Electrical Engineering)
Wade Wang Skills
- Digital Signal Processors
- Perl
- Fpga Acceleration
- Simulations
- ISA
- SystemVerilog
- Logic Design
- GPU
- Embedded Systems
- Camera
Wade Wang Summary
Wade Wang, based in San Jose, CA, US, is currently a System Design Architect (Cadence SSG System, Chiplet IP, NoC, NPU, DSP) at Cadence Design Systems. Wade Wang brings experience from previous roles at Tencent US and Qualcomm. Wade Wang holds a 1997 - 2000 Master's Degree in Very-Large-Scale Integration (VLSI) in Dept of ECE @ University of New Brunswick. With a robust skill set that includes Digital Signal Processors, Perl, Fpga Acceleration, Simulations, ISA and more. Wade Wang has 3 emails and 2 mobile phone numbers on RocketReach.
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