Hao Ji Email & Phone Number
Vice President of Research and Development @ Cadence Design Systems
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Hao Ji Location
- San Jose, CA, US
Hao Ji Work
- Vice President of Research and Development @ (February 2014 - Present)
- Product Engineer Director @ (January 2003 - January 2014)
- R and D Manager and Sr. Software Engineer @ Celestry Design Technology, Inc. (January 2001 - January 2003)
- Sr. Software Engineer @ Ultima Interconnect Technology, Inc. (March 2000 - January 2001)
Hao Ji Education
- University of California, Santa Cruz
Doctor of Philosophy (Ph.D.) (Computer Engineering)
1997-2000 - Southeast University
Master's Degree (Electrical Engineering)
1994-1997 - Southeast University
Bachelor's Degree (Electrical Engineering)
1991-1994
Hao Ji Skills
- ASIC
- EDA
- TCL
- Physical Design
- Verilog
- SoC
- Integrated Circuit Design
- IC
- Semiconductors
- VLSI
- Cadence Virtuoso
- Mixed Signal
- Simulations
- Static Timing Analysis
- Analog
- Leadership
- Engineering
- Software
- Strategic Planning
- Microsoft Office
- Product Management
- Customer Service
- Management
- Product Development
- Application Specific Integrated Circuits Asic
- Application Specific Integrated Circuits
Hao Ji Summary
- Hao Ji, based in San Jose, CA, US, is currently a Vice President of Research and Development at Cadence Design Systems. Hao Ji brings experience from previous roles at Cadence Design Systems, Celestry Design Technology, Inc. and Ultima Interconnect Technology, Inc.. Hao Ji holds a 1997 - 2000 Doctor of Philosophy (Ph.D.) in Computer Engineering @ University of California, Santa Cruz. With a robust skill set that includes ASIC, EDA, TCL, Physical Design, Verilog and more. Hao Ji has 2 emails and 1 mobile phone numbers on RocketReach.
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