Vineet Dhingra Email
Sr. Principal Design Verification Engineer @ Cadence Design Systems
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Vineet Dhingra Location
- San Jose, CA, US
Vineet Dhingra Work
- Sr. Principal Design Verification Engineer @ (August 2022 - Present)
- Sr. Principal Design Engineer @ (August 2022 - Present)
- Member of Technical Staff @ (January 2010 - July 2013)
- Principal Design Verification Engineer @ (July 2019 - July 2022)
- Senior Member of Technical Staff @ (June 2013 - July 2019)
Vineet Dhingra Education
- Centre for Development of Advanced Computing (C-DAC)
Master of Technology - MTech (Very Large Scale Integration (VLSI))
2008-2010 - The NorthCap University
Bachelor of Engineering - BE (Electronics & Instrumentation)
2004-2008 - Shaheed Rajpal DAV Public School - India
12th (Science)
2003-2004
Vineet Dhingra Summary
- Vineet Dhingra, based in San Jose, CA, US, is currently a Sr. Principal Design Verification Engineer at Cadence Design Systems. Vineet Dhingra brings experience from previous roles at Cadence Design Systems. Vineet Dhingra holds a 2008 - 2010 Master of Technology - MTech in Very Large Scale Integration (VLSI) @ Centre for Development of Advanced Computing (C-DAC). Vineet Dhingra has 3 emails on RocketReach.
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