Tejaswi Kakarna's Location
Austin, TX, US
Tejaswi Kakarna's Work
- Design Verification Engineer @ Intel Corporation
- ASIC Design and Verification Engineer @ Intel Corporation
- Graduate Validation Intern @ Intel Corporation
- Applications Engineer Intern @ Group CBS
- Teaching Assistant in Electrical Engineering @ University of North Texas
- Teaching Assistant in Physics PIC LAB @ University of North Texas
- Intern @ NSIC
- Lab Assistant @ Jawaharlal Nehru Technlogical University
Tejaswi Kakarna's Education
- University of North Texas
Masters of Science (Electrical Engineering)
2011 - 2013 - Jawaharlal Nehru Technological University
Bachelor of Technology (Electronics & Communication Engineering)
2007 - 2011
Tejaswi Kakarna's Skills
- UVM
- SystemVerilog
- Verilog
- C++
- C
- VHDL
- Computer Architecture
- Perl
- ModelSim
- FPGA
Tejaswi Kakarna's Summary
Tejaswi Kakarna, based in Austin, TX, US, is currently a Design Verification Engineer at Intel Corporation, bringing experience from previous roles at Intel Corporation, Group CBS, Inc. and University of North Texas. Tejaswi Kakarna holds a 2011 - 2013 Masters of Science in Electrical Engineering @ University of North Texas. With a robust skill set that includes UVM, SystemVerilog, Verilog, C++, C and more, Tejaswi Kakarna contributes valuable insights to the industry. Tejaswi Kakarna has 2 emails and 1 mobile phone number on RocketReach.
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