Tejas Shetty Email & Phone Number
R and D IC Design Engineer @ Broadcom
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Tejas Shetty Location
- San Jose, CA, US
Tejas Shetty Work
- 2022 -now R and D IC Design Engineer @
- 2022 -2022 Staff Engineer @
- 2020 -2022 Senior Hardware Engineer @
- 2016 -2020 SoC Design Engineer (Physical design) @
- 2015 -2016 Graphics Hardware Engineer @
- 2015 -2015 ASIC Design Engineer @ Scalable Systems Research Labs Inc.
- 2015 -2015 Applications Engineering Intern @ Altera
Tejas Shetty Education
- San Jose State University
Master's degree (Electrical and Electronics Engineering)
2013-2015 - Ramrao Adik Institute of Technology
Bachelor of Engineering - BE (Electronics Engineering)
2009-2013
Tejas Shetty Skills
- Verilog
- Cadence Virtuoso
- SystemVerilog
- FPGA
- ASIC
- Debugging
- VLSI
- Semiconductors
- SoC
- Simulations
- Scripting
- IC
- Perl
- C++
- Linux
- Unix
- Windows
- Microsoft Office
- Teamwork
- RTL Design
- Xilinx ISE
- RTL coding
- Synopsys tools
- ModelSim
- CMOS
- Synopsys VCS
- Synopsys Design Vision
- Logic Synthesis
- PCIe
- Integrated Circuit Design
- Static Timing Analysis
- Physical Design
- ICC2
- ICC
- CTS
- CTMESH
- Floorplanning
- PnR
- Conformal LEC
- Design Rule Checking (DRC)
- Layout Versus Schematic (LVS)
- Primetime
- TCL
- FEV
- Caliber
- Clock Tree Synthesis
- Timing Closure
- SerDes
- UPF
- GDS
- Digital Electronics
- Python
- AutoCAD
- Microcontrollers
- Synopsys Verdi
- C
- Embedded Systems
- Testing
- Java
- ATPG
- RCA
- Signal Integrity
- Generators
- Analog
- Instruction
- SAN
- Protocol
- Features
- Search
- Design
- Arithmetic
- Assertions
- Scan Insertion
- Signal
- Algorithms
- Structures
- Oscilloscope
- Assembly Language
- DDR2
- Timing
- Engineering
- Computer Programming
- Nios Ii
- Hardware
- Apb
- Layout Versus Schematic Lvs
- EagleCAD
- Instructions
- Operations
- Integrated Circuit
- Checks
- Courses
- Fetch
- Quartus
- I2C
- BIST
- Code
- Matching
- Interfaces
- Graphics
- PCB design
- CAD
- Design Rule Checking Drc
- Cadence
- Components
- Algorithm Design
- Challenging Environment
- Analytical Skill
- Amba
- AXI
- Virtuoso
- Code Coverage
- Design Rule Checking
- Layout Versus Schematic
Tejas Shetty Summary
- Tejas Shetty, based in San Jose, CA, US, is currently a R and D IC Design Engineer at Broadcom Inc.. Tejas Shetty brings experience from previous roles at Achronix Semiconductor Corporation and Intel Corporation. Tejas Shetty holds a 2013 - 2015 Master's degree in Electrical and Electronics Engineering @ San Jose State University. With a robust skill set that includes Verilog, Cadence Virtuoso, SystemVerilog, FPGA, ASIC and more. Tejas Shetty has 3 emails and 2 mobile phone numbers on RocketReach.
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