Suruchi Jain Email
Staff Application Engineer @ Cadence Design Systems
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Suruchi Jain Location
- Santa Clara, CA, US
Suruchi Jain Work
- Staff Application Engineer @ (September 2018 - Present)
- Principal Application Engineer @ (November 2013 - September 2018)
- Senior Asic Verification Engineer @ (June 2010 - November 2013)
- Asic Engineer @ (May 2004 - June 2010)
Suruchi Jain Education
- Rajasthan university,India
Bachelor Of Engineering (Electronics, Communications)
2001-2004
Suruchi Jain Skills
- APB
- ASIC
- AXI
- Analytical Skills
- Application-Specific Integrated Circuits (ASIC)
- Communication
- Debugging
- Embedded Systems
- Emulation
- Emulator
- FPGA
- Field-Programmable Gate Arrays (FPGA)
- Functional Verification
- I2C
- Joint Test Action Group (JTAG)
- Palladium
- Power Estimation
- Problem Solving
- Python (Programming Language)
- RTL Design
- SV
- Simvision
- SoC
- Specman
- System on a Chip (SoC)
- SystemC
- SystemVerilog
- Test Planning
- UVM
- Universal Asynchronous Receiver/Transmitter (UART)
- VLSI
- VMM
- Vera
- Verilog
- Very-Large-Scale Integration (VLSI)
Suruchi Jain Summary
- Suruchi Jain, based in Santa Clara, CA, US, is currently a Staff Application Engineer at Cadence Design Systems. Suruchi Jain brings experience from previous roles at Cadence Design Systems, Marseille Networks Inc and Einfochips. Suruchi Jain holds a 2001 - 2004 Bachelor Of Engineering in Electronics, Communications @ Rajasthan university,India. With a robust skill set that includes APB, ASIC, AXI, Analytical Skills, Application-Specific Integrated Circuits (ASIC) and more. Suruchi Jain has 2 emails on RocketReach.
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