Stephane Leclerc Email & Phone Number
Design Engineering Director @ Cadence Design Systems
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Stephane Leclerc Location
- Montreal, QC, CA
Stephane Leclerc Work
- 2017 -now Design Engineering Director @
- 2013 -2017 Senior Design Engineering Manager @
- 2000 -2013 Leader, Mixed-Signal Layout @
- 1997 -2000 Leader, Layout @ Goal Semiconductor
Stephane Leclerc Education
- HEC Montréal
Master of Business Administration (M.B.A.) (Management, Finance, Strategy, Marketing)
2000-2003 - Polytechnique Montréal
Master's Degree (M.Sc.A., Engineering Physics - MEMS)
1994-2000 - Polytechnique Montréal
Engineer's Degree (B.Ing., Engineering Physics)
1990-1994
Stephane Leclerc Skills
- CMOS
- LVS
- IC
- Physical Design
- Mixed Signal
- Analog Circuit Design
- Cadence Virtuoso
- Cadence
- PLL
- ASIC
- Analog
- DRC
- Physical Verification
- SoC
- VLSI
- Application Specific Integrated Circuits Asic
- Layout
- Very Large Scale Integration Vlsi
- Design Engineering
- Design Rule Checking Drc
- Microsoft Excel
- Leadership
- Layout Versus Schematic Lvs
- System on a Chip Soc
- Manufacturing
- Integrated Circuits Ic
- Semiconductors
- System on a Chip
- Very Large Scale Integration
- Integrated Circuits
- Design Rule Checking
- Application Specific Integrated Circuits
- Layout Versus Schematic
Stephane Leclerc Summary
- Stephane Leclerc, based in Montreal, QC, CA, is currently a Design Engineering Director at Cadence Design Systems. Stephane Leclerc brings experience from previous roles at Cadence Design Systems, PMC-Sierra and Goal Semiconductor. Stephane Leclerc holds a 2000 - 2003 Master of Business Administration (M.B.A.) in Management, Finance, Strategy, Marketing @ HEC Montréal. With a robust skill set that includes CMOS, LVS, IC, Physical Design, Mixed Signal and more. Stephane Leclerc has 2 emails on RocketReach.
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