Rushin Patel Email & Phone Number
IC Design Engineer - Chip Power Integrity @ Broadcom
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Rushin Patel Location
- San Jose, CA, US
Rushin Patel Work
- IC Design Engineer - Chip Power Integrity @ (March 2026 - Present)
- Product Engineering Specialist @ (July 2023 - March 2026)
- Sr. Principal Product Engineer @ (May 2016 - August 2023)
- Application Engineer @ (February 2015 - May 2016)
- Design Methodology Engineer @ (February 2011 - October 2014)
- Graduate student @ (January 2008 - December 2009)
Rushin Patel Education
- San José State University
MS (Electrical Engineering)
2008-2009 - PIET
BE (Electronics & Communication)
2003-2007
Rushin Patel Skills
- Synopsys tools
- Physical Design
- SoC
- ASIC
- Low-power Design
- EM/IR
- Digital IC Design
- Cadence
Rushin Patel Summary
- Rushin Patel, based in San Jose, CA, US, is currently a IC Design Engineer - Chip Power Integrity at Broadcom. Rushin Patel brings experience from previous roles at Cadence Design Systems, ANSYS Apache and LSI, an Avago Technologies Company. Rushin Patel holds a 2008 - 2009 MS in Electrical Engineering @ San José State University. With a robust skill set that includes Synopsys tools, Physical Design, SoC, ASIC, Low-power Design and more. Rushin Patel has 6 emails and 3 mobile phone numbers on RocketReach.
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