now Sr. Group Director, Software Engineering, Digital and Signoff Group @
now Group Director, Software Engineering, Digital and Signoff Group @
now Group Director, R and D, Design Group @
now Director, R and D, Analog and Mixed-Signal Group @
now Principal Engineer, Intel Architecture Group @
now Principal R and D Engineer, Implementation Group @
now Senior Member Technical Staff @ Gradient Design Automation
now Sr. Staff CAD Engineer, Microprocessor Design Group @
now Sr. Staff CAD Engineer, Design Technology @
now Sr. Staff CAD Engineer, Technology CAD @
Nanda Gopal Education
St Josephs College Arts Science
Nanda Gopal Skills
TCL
Algorithms
Static Timing Analysis
EDA
Timing
Physical Design
VLSI
SoC
Perl
C++
Simulation
IC
C
Signal Integrity
Programming
Software Development
OOP
Software Engineering
Primetime
Timing Closure
Debugging
RTL design
CAD
Strategic Planning
Management
Social Media
Integration
Project Management
System on a Chip Soc
Very Large Scale Integration Vlsi
Intel
Power
Applications
ASIC
Very Large Scale Integration
System on a Chip
Nanda Gopal Summary
Nanda Gopal, based in Saratoga, CA, US, is currently a Fellow at Cadence. Nanda Gopal brings experience from previous roles at Cadence and Synopsys Inc. Nanda Gopal holds a St Josephs College Arts Science. With a robust skill set that includes TCL, Algorithms, Static Timing Analysis, EDA, Timing and more. Nanda Gopal has 2 emails and 1 mobile phone numbers on RocketReach.
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