Mohit Patel Location
California, United States
Mohit Patel Work
- 2026 - now Sr. Principal Design Engineer @ Cadence Design Systems
- 2021 - 2026 Micro-Architect @ AMD
- 2016 - 2021 Senior ASIC Digital Logic Design Engineer @ Intel Corporation
- 2012 - 2016 Sr Graphics Hardware Design Engineer @ Intel Corporation
- 2012 - 2012 Graphic Design Intern @ Intel Corporation
- 2011 - 2011 Graduate Research Assistant @ California Smart Grid Center
- 2009 - 2009 RF Engineer Intern @ Tata Tele Business Services
Mohit Patel Education
- California State University-Sacramento
MS (Digital Design & Computer Architecture / (VLSI))
2010 - 2012 - Gujarat University
B.E (Electronics & Communication)
2005 - 2009
Mohit Patel Skills
- Computer Architecture
- Verification/ Validation
- VLSI Design/Testing
- Verilog
- system verilog
- Perl Automation
- C
- C++
- Graphic Design
- TCL
Mohit Patel Summary
Mohit Patel, based in California, United States, is currently a Sr. Principal Design Engineer at Cadence. Mohit Patel brings experience from previous roles at AMD and Intel Corporation. Mohit Patel holds a 2010 - 2012 MS in Digital Design & Computer Architecture / (VLSI) @ California State University-Sacramento. With a robust skill set that includes Computer Architecture, Verification/ Validation, VLSI Design/Testing, Verilog, system verilog and more. Mohit Patel has 5 emails and 4 mobile phone numbers on RocketReach.
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