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Mohit Patel Location
California, United States
Mohit Patel Work
2026 -now Sr. Principal Design Engineer @
2021 -2026 Micro-Architect @
2016 -2021 Senior ASIC Digital Logic Design Engineer @
2012 -2016 Sr Graphics Hardware Design Engineer @
2012 -2012 Graphic Design Intern @
2011 -2011 Graduate Research Assistant @ California Smart Grid Center
2009 -2009 RF Engineer Intern @
Mohit Patel Education
California State University-Sacramento
MS (Digital Design & Computer Architecture / (VLSI))
2010-2012
Gujarat University
B.E (Electronics & Communication)
2005-2009
Mohit Patel Skills
Computer Architecture
Verification/ Validation
VLSI Design/Testing
Verilog
system verilog
Perl Automation
C
C++
Graphic Design
TCL
RTL Verification
RTL Design
RTL Coding
Synopsys tools
PCIe
PCI Standards
Verdi
ASIC
ModelSim
VHDL
Perl
Field-Programmable Gate Arrays (FPGA)
Static Timing Analysis
Functional Verification
Simulations
Matlab
Field Programmable Gate Arrays Fpga
Microcontrollers
Microsoft Office
Cadence Virtuoso
SystemVerilog
Embedded Systems
Pspice
Proteus
Microprocessors
CMOS
Xilinx
Linux
Xilinx ISE
Python
SPICE
SoC
Place and Route
Code Coverage
Assertion Based Verification
Clock Tree Synthesis
Physical Design
Questa
Emulation
Calibre
Object Oriented Programming
UVM
Field Programmable Gate Arrays
Mohit Patel Summary
Mohit Patel, based in California, United States, is currently a Sr. Principal Design Engineer at Cadence. Mohit Patel brings experience from previous roles at AMD and Intel Corporation. Mohit Patel holds a 2010 - 2012 MS in Digital Design & Computer Architecture / (VLSI) @ California State University-Sacramento. With a robust skill set that includes Computer Architecture, Verification/ Validation, VLSI Design/Testing, Verilog, system verilog and more. Mohit Patel has 4 emails and 3 mobile phone numbers on RocketReach.
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