Ming Cheung Location
Sunnyvale, CA, US
Ming Cheung Work
- 2002 - now Senior Principal Engineer @ Cadence Design Systems
- 1995 - 2002 ASIC Design Manager @ Lucent Technologies/Agere
- 1995 - 1995 Lead Contractor @ Seagate Technology
- 1985 - 1995 Design Project Lead for high end mainframes @ IBM
Ming Cheung Education
- Syracuse University
Master’s Degree (Electrical Engineering)
1986 - 1989 - University of Missour-Rolla
Bachelor’s Degree (Electrical Engineering)
1983 - 1985
Ming Cheung Skills
- Cadence RC and Genus tool for logic synthesis & DFT insertion
- Logic Synthesis
- Encounter place & route tool of Cadence Design Systems
- Encounter Timing Systems of Cadence
- Primetime STA analysis tool of Synopsys
- DDR3 & DDR4 IP
- FPGA
- JTAG
- Celtic noise analysis
- Conformal LEC
Ming Cheung Summary
Ming Cheung, based in Sunnyvale, CA, US, is currently a Senior Principal Engineer at Cadence Design Systems. Ming Cheung brings experience from previous roles at Lucent Technologies/Agere, Seagate Technology and IBM. Ming Cheung holds a 1986 - 1989 Master’s Degree in Electrical Engineering @ Syracuse University. With a robust skill set that includes Cadence RC and Genus tool for logic synthesis & DFT insertion, Logic Synthesis, Encounter place & route tool of Cadence Design Systems, Encounter Timing Systems of Cadence, Primetime STA analysis tool of Synopsys and more. Ming Cheung has 3 emails and 2 mobile phone numbers on RocketReach.
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