2021 -
now Visiting Scientist in TID Integrated Circuits group - ASIC Designer @
2022 -
now CASE Senior Scientist @
2018 -
2025 NAISE Senior Fellow @
2019 -
2021 Integrated Circuit Designer for CERN Large Hadron Collider @
2016 -
2017 Hardware Engineer - FPGA Designer @
2013 -
2016 Senior Manager of Digital Design @
2002 -
2013 Senior IP Design Engineer @
1980 -
2002 Member of Technical Staff @
Mike Hammer Education
Purdue University
Northwestern University
University of Illinois Chicago
Mike Hammer Skills
FPGA
Verilog
ASIC
VHDL
Altera
SoC
RTL design
RTL coding
Timing Closure
EDA
ModelSim
Xilinx
Static Timing Analysis
VLSI
Integrated Circuit Design
CPLD
SERDES
Ethernet
Logic Design
Simulations
Debugging
Schematic Capture
Primetime
Hardware Architecture
Functional Verification
PCIe
TCL
SystemVerilog
Semiconductors
Mike Hammer Summary
Mike Hammer, based in Lemont, IL, US, is currently a Principal Electrical Engineer at Argonne National Laboratory. Mike Hammer brings experience from previous roles at SLAC National Accelerator Laboratory, University of Chicago, Northwestern University and Fermilab. Mike Hammer holds a Purdue University. With a robust skill set that includes FPGA, Verilog, ASIC, VHDL, Altera and more. Mike Hammer has 6 emails and 2 mobile phone numbers on RocketReach.
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