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Loc Tran Location
Los Gatos, CA, US
Loc Tran Work
2023 -now Layout-Mask Design Engineer @
2019 -2024 Principal Engineer, IC layout for RFIC-Analog-Mixed Signal. @
2017 -2019 Sr. RFIC and Analog-Mixed signal Layout Design Engineer (Consultant) @
2017 -2018 Sr. IC Analog Layout Engineer (Consultant) @ Google-Verily Life Sciences
2010 -2017 Sr. IC Layout Designer @
2007 -2010 Sr. IC layout designer @
2006 -2007 Sr. IC Analog layout designer @
2003 -2006 Sr. SRAM Mask Designer @
2001 -2003 Sr. IC layout Designer @
1999 -2001 Sr. IC Layout Designer @ Sibyte
1995 -1999 IC Analog-Mixed Signal and Cams-RFs layout Design expertise @
Loc Tran Education
San Jose State University
(Electrical and Electronics Engineering)
Quinsigamond Community College
(Electrical and Electronics Engineering)
Loc Tran Skills
Cadence Virtuoso
Floorplanning
SRAM
Radio Frequency Rf
Layout Tools
Layout Versus Schematic Lvs
Debugging
System On A Chip Soc
Rfic
5G
Microprocessors
Processors
ASIC
Analog Layout Design
Cadence
Vxl
ADCs
Integrated Circuits Ic
Mixed Signal
Rfic Mixed Signal Analog
CMOS
Design for Manufacturing
SERDES
Fast Leaner
Floorplanning Layout Design
IC layout
Low Noise Amplifier Lna
DRC
Semiconductors
Physical Design
Wrf
Very Large Scale Integration Vlsi
Transistors
Phase Locked Loop Pll
System on a Chip
Layout Versus Schematic
Integrated Circuits
Sram Ic Layout
Radio Frequency
Low Noise Amplifier
Phase Locked Loop
Very Large Scale Integration
Loc Tran Summary
Loc Tran, based in Los Gatos, CA, US, is currently a Layout-Mask Design Engineer at NVIDIA. Loc Tran brings experience from previous roles at Samsung Electronics America, Google-Verily Life Sciences and Oracle. Loc Tran holds a San Jose State University. With a robust skill set that includes Cadence Virtuoso, Floorplanning, SRAM, Radio Frequency Rf, Layout Tools and more. Loc Tran has 4 emails and 2 mobile phone numbers on RocketReach.
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