Principal Engineer, IC layout for RFIC-Analog-Mixed Signal. @ (April 2019 - August 2024)
Sr. RFIC and Analog-Mixed signal Layout Design Engineer (Consultant) @ (November 2017 - April 2019)
Sr. IC Analog Layout Engineer (Consultant) @ Google-Verily Life Sciences (September 2017 - January 2018)
Sr. IC Layout Designer @ (January 2010 - October 2017)
Sr. IC layout designer @ (February 2007 - January 2010)
Sr. IC Analog layout designer @ (January 2006 - February 2007)
Sr. SRAM Mask Designer @ (June 2003 - January 2006)
Sr. IC layout Designer @ (January 2001 - June 2003)
Sr. IC Layout Designer @ Sibyte (February 1999 - January 2001)
IC Analog-Mixed Signal and Cams-RFs layout Design expertise @ (May 1995 - February 1999)
Loc Tran Education
San José State University
(Electrical and Electronics Engineering)
Quinsigamond Community College
(Electrical and Electronics Engineering)
Loc Tran Skills
Cadence Virtuoso
Floorplanning
SRAM
Radio Frequency Rf
Layout Tools
Layout Versus Schematic Lvs
Debugging
System On A Chip Soc
Rfic
5G
Microprocessors
Processors
ASIC
Analog Layout Design
Cadence
Vxl
ADCs
Integrated Circuits Ic
Mixed Signal
Rfic Mixed Signal Analog
CMOS
Design for Manufacturing
SERDES
Fast Leaner
Floorplanning Layout Design
IC layout
Low Noise Amplifier Lna
DRC
Semiconductors
Physical Design
Wrf
Very Large Scale Integration Vlsi
Transistors
Phase Locked Loop Pll
System on a Chip
Layout Versus Schematic
Integrated Circuits
Sram Ic Layout
Radio Frequency
Low Noise Amplifier
Phase Locked Loop
Very Large Scale Integration
Loc Tran Summary
Loc Tran, based in Los Gatos, CA, US, is currently a Layout-Mask Design Engineer at NVIDIA. Loc Tran brings experience from previous roles at Samsung Electronics America, Google-Verily Life Sciences and Oracle. Loc Tran holds a San José State University. With a robust skill set that includes Cadence Virtuoso, Floorplanning, SRAM, Radio Frequency Rf, Layout Tools and more. Loc Tran has 2 emails and 2 mobile phone numbers on RocketReach.
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