John Tseng Email & Phone Number
Senior Design Engineering Architect @ Cadence Design Systems
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John Tseng Location
- Redwood City, CA, US
John Tseng Work
- Senior Design Engineering Architect @ (June 2026 - Present)
- Sr Staff Silicon Design Engineer @ (March 2025 - April 2026)
- Sr CAD and PD Lead @ (April 2023 - March 2025)
- Senior Member of Technical Staff @ (March 2020 - April 2023)
- Technical Director, VLSI @ (July 2019 - March 2020)
- Director, VLSI Methdology @ (May 2019 - July 2019)
- Sr Methodology Engineer @ (September 2014 - May 2019)
- Sr Methodology Engineer @ Altera (October 2014 - December 2015)
- Engineer @ (September 2010 - October 2014)
- Sr. Engineering Manager @ (May 2014 - September 2014)
- Sr. Engineering Manager @ (January 2012 - May 2014)
- Engineering Manager, Physical Design @ (September 2011 - December 2011)
- Senior Principle Engineer @ (September 2010 - September 2011)
- Senior Principle Engineer @ (October 2007 - September 2010)
- Senior Methodology Lead @ (August 2005 - October 2007)
- ASIC CAD Manager @ (May 2004 - July 2005)
- Senior Principle Engineer @ (January 2004 - January 2005)
- ASIC CAD Manager @ PA Semi (January 2004 - January 2005)
- Director of Physical Design @ Raza Microelectronics (January 2002 - May 2004)
- Engineer In Residence @ Raza Foundries (November 2001 - January 2002)
- Senior Engineer @ Nishan Systems (April 2000 - November 2001)
- Senior Engineer @ (October 1995 - April 2000)
- Design Engineer @ (May 1995 - October 1995)
John Tseng Education
- University of California, Berkeley
BS (Electrical Engineer Computer Science)
1991-1995
John Tseng Skills
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- C (Programming Language)
- C++
- Cadence
- Cadence Virtuoso
- Clock Tree Synthesis
- Computer Science
- Cross-functional Team Leadership
- Debugging
- EDA
- Electrical Engineering
- Field-Programmable Gate Arrays (FPGA)
- High Performance Computing (HPC)
- IC
- Integrated Circuit Design
- Integration
- LaTeX
- Linux
- Linux Kernel
- Logic Design
- Logic Synthesis
- Microprocessors
- Microsoft Office
- Perl
- Physical Design
- Place & Route
- Platform LSF
- Processors
- Product Development
- Python (Programming Language)
- RTL Design
- SPICE
- Semiconductors
- Shell Scripting
- SoC
- Software Development
- Static Timing Analysis
- Synopsys IC Compiler
- Synopsys Primetime
- System Architecture
- System on a Chip (SoC)
- SystemVerilog
- TCL
- VHDL
- VLSI
- VLSI CAD
- Verilog
- Virtuoso
- Semiconductor Industry
- Enterprise Software
- Intel
- Project Management
- Field Programmable Gate Arrays Fpga
- Testing
- System on a Chip Soc
- Silicon
- Functional Verification
- Application Specific Integrated Circuits Asic
- Cross Functional Team Leadership
- High Performance Computing Hpc
- Place And Route
- Start Up Environment
- Lsf
- Application Specific Integrated Circuits
- System on a Chip
- Field Programmable Gate Arrays
- High Performance Computing
John Tseng Summary
- John Tseng, based in Redwood City, CA, US, is currently a Senior Design Engineering Architect at Cadence. John Tseng brings experience from previous roles at Tesla, Esperanto Technologies, Inc, Cerebras Systems and Intel Corporation. John Tseng holds a 1991 - 1995 BS in Electrical Engineer Computer Science @ University of California, Berkeley. With a robust skill set that includes ASIC, Application-Specific Integrated Circuits (ASIC), C (Programming Language), C++, Cadence and more. John Tseng has 3 emails and 3 mobile phone numbers on RocketReach.
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