Jia Chen Location
- San Jose, CA, US
Jia Chen Work
- 2013 - now Senior Design Engineer @
- 2005 - 2013 Senior Analog Engineer @ Chrontel Inc.
Jia Chen Education
- Arizona State University
Master of Science Electrical Engineering (MSEE) (Solid State Electronics (GPA: 3.80))
2001 - 2002
Jia Chen Skills
- PLL
- Spectre
- Mixed Signal
- CMOS
- Analog Circuit Design
- IC
- Cadence Virtuoso
- Analog
- ASIC
- Circuit Design
- Cadence Spectre
- SPICE
- SpectreRF
Jia Chen Summary
- Jia Chen, based in San Jose, CA, US, is currently a Senior Design Engineer at NVIDIA. Jia Chen brings experience from previous roles at Chrontel Inc.. Jia Chen holds a 2001 - 2002 Master of Science Electrical Engineering (MSEE) in Solid State Electronics (GPA: 3.80) @ Arizona State University. With a robust skill set that includes PLL, Spectre, Mixed Signal, CMOS, Analog Circuit Design and more. Jia Chen has 2 emails and 1 mobile phone numbers on RocketReach.
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