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Jared Lee Location
California, United States
Jared Lee Work
2020 -now AE Director @
2016 -2020 Senior AE Manager @
2007 -2016 Staff Application Engineer @
1997 -2007 Senior Hardware Design Engineer @
Jared Lee Education
University of Phoenix
BSIT
2005-2006
Mesa Community College
EET
1994-2003
Mesa Community College
CAD
1994-2003
Jared Lee Skills
Clock Tree Synthesis
Engineering Management
New Business Development
Process Improvement
Business Transformation
IC
Integrated Circuit Design
Semiconductors
ASIC
Processors
RTL design
Microprocessors
Formal Verification
Simulations
EDA
LVS
SoC
Mask Design
Floorplanning
VHDL
TCL
Go-to-market Strategy
APR
Place & Route
Verilog
Silicon
Physical Design
Account Management
Project Management
Sales Management
DRC
Cadence
Mixed Signal
Debugging
VLSI
Static Timing Analysis
Perl
Low-power Design
Application-Specific Integrated Circuits (ASIC)
System on a Chip (SoC)
Integrated Circuits (IC)
Very-Large-Scale Integration (VLSI)
Application Specific Integrated Circuits Asic
Microsoft Excel
Graphic Design
Place and Route
System on a Chip Soc
Go to Market Strategy
Integrated Circuit
Integrated Circuits Ic
Testing
Embedded Systems
Engineering
Low Power Design
Very Large Scale Integration Vlsi
Hardware
Integration
Application Specific Integrated Circuits
Integrated Circuits
System on a Chip
Very Large Scale Integration
Jared Lee Summary
Jared Lee, based in California, United States, is currently a AE Director at Cadence Design Systems. Jared Lee brings experience from previous roles at Cadence Design Systems and Intel. Jared Lee holds a 2005 - 2006 BSIT @ University of Phoenix. With a robust skill set that includes Clock Tree Synthesis, Engineering Management, New Business Development, Process Improvement, Business Transformation and more. Jared Lee has 2 emails on RocketReach.
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