Jaebum Lee's Location

San Jose, California, United States

Jaebum Lee's Work

Jaebum Lee's Education

  • University of Minnesota-Twin Cities

    PhD (Computer Science and Engineering)

    1990 - 1995
  • University of Minnesota-Twin Cities

    MS (Computer Science and Engineering)

    1987 - 1989
  • Seoul National University

    BS (Computer Science and Engineering)

    1983 - 1987

Jaebum Lee's Skills

  • Physical Design
  • Timing Closure
  • Floorplanning
  • Static Timing Analysis
  • SoC
  • Primetime
  • ASIC
  • Low Power Design
  • Physical Verification
  • LVS

Jaebum Lee's Summary

Jaebum Lee, based in San Jose, California, United States, is currently a Sr. Physical Design Manager at Marvell Semiconductor, bringing experience from previous roles at Fast Chip and Hewlett-Packard /Agilent Technologies. Jaebum Lee holds a 1990 - 1995 PhD in Computer Science and Engineering @ University of Minnesota-Twin Cities. With a robust skill set that includes Physical Design, Timing Closure, Floorplanning, Static Timing Analysis, SoC and more, Jaebum Lee contributes valuable insights to the industry. Jaebum Lee has 2 emails on RocketReach.

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