Harshit Mehta Email
Senior Principal Engineer @ Cadence Design Systems
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Harshit Mehta Location
- Gurugram, HR, IN
Harshit Mehta Work
- 2024 -now Senior Principal Engineer @
- 2021 -2024 Principal Engineer @
- 2018 -2021 Lead Engineer @
- 2013 -2018 Verification Engineer @
Harshit Mehta Education
- ACTS CDAC, Pune
PG Diploma (VLSI)
2013-2013 - Gurgaon College of Engg.
Bachelor of Technology (B.Tech.) (Event Head and participated at several seminars. Active Participation in several sport and cultural program at college and school level.)
2008-2012
Harshit Mehta Skills
- Digital Designs
- Verilog
- VLSI
- VHDL
- system verilog
- ModelSim
- Questa
- Xilinx ISE
- ngspice
- CMOS
- GNU/Linux
- micromagic
- Network Engineering
- USB
- VMM
- C++
- PCI-X
- Memory
- SystemVerilog
- AMBA AHB
- NCSim
- System On A Chip Soc
- Perl
- Application Specific Integrated Circuits Asic
- Universal Verification Methodology Uvm
- Pci X
- Very Large Scale Integration Vlsi
- Universal Verification Methodology
- Application Specific Integrated Circuits
- System on a Chip
- Very Large Scale Integration
Harshit Mehta Summary
- Harshit Mehta, based in Gurugram, HR, IN, is currently a Senior Principal Engineer at Cadence. Harshit Mehta brings experience from previous roles at Cadence and AppliedMicro. Harshit Mehta holds a 2013 - 2013 PG Diploma in VLSI @ ACTS CDAC, Pune. With a robust skill set that includes Digital Designs, Verilog, VLSI, VHDL, system verilog and more. Harshit Mehta has 1 emails on RocketReach.
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