Harshit Mehta Email
Senior Principal Engineer @ Cadence Design Systems
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Harshit Mehta Location
- Gurugram, HR, IN
Harshit Mehta Work
- Senior Principal Engineer @ (July 2024 - Present)
- Principal Engineer @ (June 2021 - June 2024)
- Lead Engineer @ (March 2018 - June 2021)
- Verification Engineer @ (October 2013 - February 2018)
Harshit Mehta Education
- ACTS CDAC, Pune
PG Diploma (VLSI)
2013-2013 - Gurgaon College of Engg.
Bachelor of Technology (B.Tech.) (Electronics and Communications Engineering)
2008-2012
Harshit Mehta Skills
- Application-Specific Integrated Circuits (ASIC)
- Digital Designs
- Emulation
- Ethernet
- GNU/Linux
- Ixia
- ModelSim
- Palladium
- Perl
- Spirent Test Center
- System on a Chip (SoC)
- SystemVerilog
- Universal Verification Methodology (UVM)
- VHDL
- VLSI
- Verilog
- Very-Large-Scale Integration (VLSI)
- system verilog
- Questa
- Xilinx ISE
- ngspice
- CMOS
- micromagic
- Network Engineering
- USB
- VMM
- C++
- PCI-X
- Memory
- AMBA AHB
- NCSim
- System On A Chip Soc
- Application Specific Integrated Circuits Asic
- Universal Verification Methodology Uvm
- Pci X
- Very Large Scale Integration Vlsi
- Universal Verification Methodology
- Application Specific Integrated Circuits
- System on a Chip
- Very Large Scale Integration
Harshit Mehta Summary
- Harshit Mehta, based in Gurugram, HR, IN, is currently a Senior Principal Engineer at Cadence. Harshit Mehta brings experience from previous roles at Cadence and AppliedMicro. Harshit Mehta holds a 2013 - 2013 PG Diploma in VLSI @ ACTS CDAC, Pune. With a robust skill set that includes Application-Specific Integrated Circuits (ASIC), Digital Designs, Emulation, Ethernet, GNU/Linux and more. Harshit Mehta has 1 emails on RocketReach.
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