Gil Peled Email & Phone Number
Application Engineer Architect, Verification @ Cadence Design Systems
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Gil Peled Work
- 2020 -now Application Engineer Architect, Verification @
- 2017 -2020 ASIC Design-Verification Manager @
- 2015 -2017 ASIC Design-Verification Lead @
- 2012 -2015 ASIC Design-Verification Lead @
- 2006 -2012 ASIC Design-Verification Lead @ Zoran
- 2004 -2006 ASIC Verification Engineer @
Gil Peled Education
- Ben-Gurion University of the Negev
Bachelor of Science (BSc) (Electrical, Electronics and Communications Engineering)
2001-2005
Gil Peled Skills
- SystemVerilog
- Semiconductors
- Embedded Systems
- ASIC
- AMBA AHB
- Logic Design
- RTL coding
- VLSI
- SoC
- Verilog
- FPGA
- NCSim
- Functional Verification
- C
- Specman
- Debugging
- Perl
- RTL design
- Application Specific Integrated Circuits
Gil Peled Summary
- Gil Peled, is currently a Application Engineer Architect, Verification at Cadence Design Systems. Gil Peled brings experience from previous roles at Mobileye, Intel Corporation, Qualcomm and Zoran. Gil Peled holds a 2001 - 2005 Bachelor of Science (BSc) in Electrical, Electronics and Communications Engineering @ Ben-Gurion University of the Negev. With a robust skill set that includes SystemVerilog, Semiconductors, Embedded Systems, ASIC, AMBA AHB and more. Gil Peled has 2 emails and 1 mobile phone numbers on RocketReach.
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