Eric Chao Email & Phone Number
Sr. Principal Engineer @ Palo Alto Networks
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Eric Chao Location
- San Jose, CA, US
Eric Chao Work
- Sr. Principal Engineer @ (November 2021 - Present)
- Principal Engineer @ (October 2019 - Present)
- Sr Staff FPGA and ASIC Engineer @ (June 2018 - Present)
- Senior FPGA Engineer @ (September 2016 - May 2018)
- Senior FPGA Engineer @ F5 Networks (September 2011 - September 2016)
- FPGA Hardware Design Engineer @ (September 2007 - September 2011)
- Hardware Engineer Co-op @ (January 2006 - August 2006)
Eric Chao Education
- University of Michigan
B.S. (Electrical Engineering)
2003-2007
Eric Chao Skills
- FPGA
- Debugging
- Verilog
- SystemVerilog
- Verification
- Altera
- Xilinx
- Perl
- C++
- Hardware
- Testing
- ASIC
- VHDL
- Microsoft Office
- SQL
Eric Chao Summary
- Eric Chao, based in San Jose, CA, US, is currently a Sr. Principal Engineer at Palo Alto Networks. Eric Chao brings experience from previous roles at Palo Alto Networks, Quantlab Financial, LLC and F5 Networks. Eric Chao holds a 2003 - 2007 B.S. in Electrical Engineering @ University of Michigan. With a robust skill set that includes FPGA, Debugging, Verilog, SystemVerilog, Verification and more. Eric Chao has 3 emails and 2 mobile phone numbers on RocketReach.
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