Eric Chao Location
San Jose, CA, US
Eric Chao Work
- 2021 - now Sr. Principal Engineer @ Palo Alto Networks
- 2019 - now Principal Engineer @ Palo Alto Networks
- 2018 - now Sr Staff FPGA and ASIC Engineer @ Palo Alto Networks
- 2016 - 2018 Senior FPGA Engineer @ Quantlab Group
- 2011 - 2016 Senior FPGA Engineer @ F5 Networks
- 2007 - 2011 FPGA Hardware Design Engineer @ Cisco
- 2006 - 2006 Hardware Engineer Co-op @ Cisco
Eric Chao Education
- University of Michigan
B.S. (Electrical Engineering)
2003 - 2007
Eric Chao Skills
- FPGA
- Debugging
- Verilog
- SystemVerilog
- Verification
- Altera
- Xilinx
- Perl
- C++
- Hardware
Eric Chao Summary
Eric Chao, based in San Jose, CA, US, is currently a Sr. Principal Engineer at Palo Alto Networks. Eric Chao brings experience from previous roles at Palo Alto Networks, Quantlab Financial, LLC and F5 Networks. Eric Chao holds a 2003 - 2007 B.S. in Electrical Engineering @ University of Michigan. With a robust skill set that includes FPGA, Debugging, Verilog, SystemVerilog, Verification and more. Eric Chao has 4 emails and 2 mobile phone numbers on RocketReach.
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