Dharmendra Goyal Email & Phone Number
Principal Engineer @ Cadence Design Systems
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Dharmendra Goyal Location
- San Jose, CA, US
Dharmendra Goyal Work
- 2013 -now Principal Engineer @
- 2012 -2013 Senior Engineer @
- 2010 -2012 Tech Lead @
- 2006 -2010 Sr. Design Engineer @
- 2004 -2006 Design Engineer @
Dharmendra Goyal Education
- Indian Institute of Technology (Banaras Hindu University), Varanasi
M.Tech (VLSI)
2002-2004 - LNCT
Bachelor of Engineering (BE) (Electronic & Communication)
1998-2002
Dharmendra Goyal Skills
- ASIC
- Static Timing Analysis
- SoC
- Physical Design
- VLSI
- Timing Closure
- Semiconductors
- Management
- Java
- Troubleshooting
- Microsoft Word
- Engineering
- Strategy
- Graphic Design
Dharmendra Goyal Summary
- Dharmendra Goyal, based in San Jose, CA, US, is currently a Principal Engineer at Cadence Design Systems. Dharmendra Goyal brings experience from previous roles at Infotech Enterprises EMEA, ST Microelectronics, NXP Semiconductors and Wipro Technologies. Dharmendra Goyal holds a 2002 - 2004 M.Tech in VLSI @ Indian Institute of Technology (Banaras Hindu University), Varanasi. With a robust skill set that includes ASIC, Static Timing Analysis, SoC, Physical Design, VLSI and more. Dharmendra Goyal has 2 emails and 2 mobile phone numbers on RocketReach.
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