David Downey Email & Phone Number
Hardware Engineering Architect @ Cadence Design Systems
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David Downey Location
- San Jose, CA, US
David Downey Work
- Hardware Engineering Architect @ (April 2019 - Present)
- Senior Principal Hardware Engineer @ (November 2016 - April 2019)
- Principal Design and Verification Engineer @ (June 2012 - November 2016)
- Lead Application Engineer @ (June 2010 - November 2016)
- Verification Consultant @ (June 2007 - September 2010)
- Asic and Fpga Design Engineer @ (August 2004 - June 2007)
- Design Engineer @ (June 2000 - May 2003)
David Downey Education
- Institute for System Level Integration
(Design)
1998-2000 - University of Strathclyde
Bachelor of Engineering (Electrical Engineering)
1994-1998
David Downey Skills
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- C (Programming Language)
- C++
- Emulation
- FPGA
- Field-Programmable Gate Arrays (FPGA)
- Formal Verification
- Functional Verification
- IC
- Leadership
- Logic Synthesis
- Low-power Design
- MIPI
- Make
- PCIe
- Perl
- Python (Programming Language)
- RTL Design
- Specman
- Static Timing Analysis
- System on a Chip (SoC)
- SystemVerilog
- Team Building
- UVM
- VHDL
- Xilinx
David Downey Summary
- David Downey, based in San Jose, CA, US, is currently a Hardware Engineering Architect at Cadence Design Systems. David Downey brings experience from previous roles at Cadence Design Systems and Verilab. David Downey holds a 1998 - 2000 Institute for System Level Integration. With a robust skill set that includes ASIC, Application-Specific Integrated Circuits (ASIC), C (Programming Language), C++, Emulation and more. David Downey has 1 mobile phone numbers on RocketReach.
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