Chien Chen Email & Phone Number
Verification Architect @ Arteris
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Chien Chen Location
- Fremont, CA, US
Chien Chen Work
- 2019 -now Verification Architect @
- 2015 -2019 Sr Manager, ASIC Verification @
- 2014 -2015 Sr. Manager @
- 2014 -2014 Sr Manager @
- 2012 -2014 Design Manager @
- 2008 -2012 Manager ASCI Verification @ SandForce
- 2008 -2008 Principal Engineer @ MagnaChip Semiconductors
- 2006 -2007 Manager @
- 2003 -2006 Director and Manager @
- 2003 -2006 Section Manager @
- 2005 -2006 Product Development Manager @ AvagoTechnologies
- 2000 -2003 Director @ RedSwitch, Inc.
- 1990 -2000 Manager @ HaL Computers
- 1990 -2000 Engineer and Manager @
Chien Chen Education
- University of California, Berkeley
Ph. D. (Computer Architecture)
1984-1991 - Princeton University
BSEE (EECS)
1980-1984 - Tsinghua University 1978-1978
Chien Chen Skills
- Product Development
- Engineering Management
- Verilog
- Semiconductors
- Architectures
- FPGA
- RTL Design
- Perl
- Firmware
- Hardware Architecture
- Processors
- Embedded Software
- Management
- ASIC/SOC
- ASIC
- Architecture
- Debugging
- EDA
- Embedded Systems
- Functional Verification
- IC
- Leadership
- Microprocessors
- PCIe
- SoC
- SystemVerilog
- VLSI
- Graphic Design
- Customer Service
- Strategy
- Project Management
- Strategic Planning
- Business Analysis
Chien Chen Summary
- Chien Chen, based in Fremont, CA, US, is currently a Verification Architect at Arteris IP. Chien Chen brings experience from previous roles at SK hynix memory solutions inc., Seagate Technology, Avago Technologies and LSI Corporation. Chien Chen holds a 1984 - 1991 Ph. D. in Computer Architecture @ University of California, Berkeley. With a robust skill set that includes Product Development, Engineering Management, Verilog, Semiconductors, Architectures and more. Chien Chen has 6 emails and 3 mobile phone numbers on RocketReach.
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