Principal Design Engineer @ (July 2022 - August 2022)
Lead Design Engineer @ (September 2019 - July 2022)
Physical Design Engineer @ (October 2015 - September 2019)
Physical Implementation Intern @ (July 2015 - October 2015)
Systems and Solution Business(SSB) Intern @ (June 2013 - August 2013)
Buyan Li Education
University of Michigan
Master of Science (M.S.) (Electrical Engineering)
2013-2015
University of Iowa
Bachelor of Science (B.S.) (Electrical Engineering)
2009-2013
Buyan Li Skills
C++
Verilog
C
ASIC
VLSI
Cadence Virtuoso
Computer Architecture
FPGA
SoC
EDA
SystemVerilog
Physical Design
VHDL
RTL Verification
Python
RTL Design
Cadence Encounter
Perl
HSPICE
PrimeTime
PrimePower
Shell Scripting
Bash
UVM
Digital IC Design
Makefile
Place & Route
Functional Verification
CPU design
SRAM
DRAM
Tcl
Calibre
DRC
LVS
Mixed-Signal IC Design
IC Layout
Design Verification
Sysnopsys Design Compiler (DC)
Synopsys ICC
NC-Verilog
MIPS
DFT
ARM
Cache Coherency
TSV
3D Stack
Redhawk
Cadence Innovus
StarRC
MAP
PowerPoint
Business Analysis
Test Cases
Leadership
Illustrator
Research
Process Improvement
Management
Computer Hardware
Design
Sysnopsys Design Compiler Dc
Mixed Signal Ic Design
Place And Route
Nc Verilog
Sysnopsys Design Compiler
Buyan Li Summary
Buyan Li, based in Austin, TX, US, is currently a Senior ASIC Design Engineer at NVIDIA. Buyan Li brings experience from previous roles at Cadence Design Systems, TSMC North America and Tezzaron Semiconductor. Buyan Li holds a 2013 - 2015 Master of Science (M.S.) in Electrical Engineering @ University of Michigan. With a robust skill set that includes C++, Verilog, C, ASIC, VLSI and more. Buyan Li has 3 emails and 1 mobile phone numbers on RocketReach.
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