Ancy M Email
Principal Design Engineer @ Cadence Design Systems
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Ancy M Location
- Bengaluru, KA, IN
Ancy M Work
- 2024 -now Principal Design Engineer @
- 2020 -2025 Lead Design Engineer @
- 2017 -2020 Senior Technical Analyst @
- 2011 -2016 Hardware Design Engineer @
- 2009 -2011 Project Engineer @
Ancy M Education
- Anna University Chennai 2004-2008
- St. Joseph's Higher Secondary School Kallody 2002-2004
Ancy M Skills
- Pattern Development
- VLSI
- ASIC
- FPGA
- Semiconductor Industry
- DFT
- Digital IC Design
- RTL Coding
- VHDL
- Semiconductors
- Verilog
- System on a Chip (SoC)
- Scan Insertion
- Automatic Test Pattern Generation (ATPG)
- MBIST
- memory bist
- GLS
- Gate Level Simulation
Ancy M Summary
- Ancy M, based in Bengaluru, KA, IN, is currently a Principal Design Engineer at Cadence. Ancy M brings experience from previous roles at Cadence, UST Global, Wipro and National Aerospace Laboratories, Bangalore. Ancy M holds a 2004 - 2008 Anna University Chennai. With a robust skill set that includes Pattern Development, VLSI, ASIC, FPGA, Semiconductor Industry and more. Ancy M has 2 emails on RocketReach.
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