Ajith R's Location
Bengaluru, KA, IN
Ajith R's Work
- Principal Engineer @ Cadence Design Systems
- Staff ASIC Design Engr @ Infinera
- Senior Design Engineer II @ Synopsys Inc
- Senior Member Of Technical Staff - II @ Rambus
- Senior Member Of Technical Staff @ Rambus
- MTS @ Rambus
- verification engineer @ Wafer Space - An ACL Digital Company
- ASIC Engineer @ eInfochips (An Arrow Company)
- contractor @ Imagination Technologies
Ajith R's Education
- PESIT ,Bangalore
B.E (Telecommunication)
2006 - 2010 - Krupanidhi college
12th
2004 - 2006
Ajith R's Skills
- SystemVerilog
- UVM
- AMBA AHB
- Verilog
- Hardware Description Language
- EDA
- ModelSim
- C++
- Ddr3/4
- Functional Verification
Ajith R's Summary
Ajith R, based in Bengaluru, KA, IN, is currently a Principal Engineer at Cadence Design Systems, bringing experience from previous roles at Infinera, Synopsys Inc and Rambus. Ajith R holds a 2006 - 2010 B.E in Telecommunication @ PESIT ,Bangalore. With a robust skill set that includes SystemVerilog, UVM, AMBA AHB, Verilog, Hardware Description Language and more, Ajith R contributes valuable insights to the industry. Ajith R has 2 emails on RocketReach.
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