1992 -
1994 Intern @ Minnesota Supercomputer Institute
1993 -
1993 Intern @
Yuet Li Education
University of Minnesota-Twin Cities
Master of Science (MS) (Electrical and Electronics Engineering)
1994
-
1996
Yuet Li Skills
Debugging
ASIC
SoC
Semiconductors
Microprocessors
Verilog
VLSI
Circuit Design
IC
RTL design
Simulations
Static Timing Analysis
PowerPoint
System On A Chip Soc
Perl
Photoshop
Strategy
Power Modeling
Power Optimization
Integrated Circuits Ic
Application Specific Integrated Circuits Asic
Customer Service
Low Power Design
Very Large Scale Integration Vlsi
System on a Chip
Application Specific Integrated Circuits
Very Large Scale Integration
Integrated Circuits
Yuet Li Summary
Yuet Li, based in Fremont, CA, US, is currently a Senior Principal Engineer at Altera at Altera. Yuet Li brings experience from previous roles at Intel Corporation, Broadcom, Next generation Intel Xeon-Phi processor design Intel Corporation and 1st Intel Xeon Phi co-processor for HPC Intel Corporation. Yuet Li holds a 1994 - 1996 Master of Science (MS) in Electrical and Electronics Engineering @ University of Minnesota-Twin Cities. With a robust skill set that includes Debugging, ASIC, SoC, Semiconductors, Microprocessors and more. Yuet Li has 2 emails on RocketReach.
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