Yiwei Chen Email & Phone Number

Yiwei Chen Skills

• Timing Closure
• Static Timing Analysis
• Primetime
• SoC
• Low Power Design
• Logic Design
• ASIC
• Physical Design
• Floorplanning
• Physical Verification
• Clock Tree Synthesis
• LVS
• Verilog
• Microprocessors
• EDA
• Logic Synthesis
• Formal Verification
• TCL
• DRC
• IC
• DFT
• ARM
• Parasitic Extraction
• Debugging
• ATPG
• Synopsys tools
• Place
• Perl
• SPICE
• Power Management
• Signal Integrity
• BIST
• Power Analysis
• PCIe
• PLL
• Digital Signal Processors
• Low-power Design
• Manufacturing
• Embedded Systems
• Sales
• Project Management
• Very Large Scale Integration Vlsi
• Integrated Circuit Design
• Semiconductors
• Microsoft Office
• Microsoft Word
• Photoshop
• Very Large Scale Integration