Gaurav Jalan Email & Phone Number
VP Engineering @ Marvell India
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Gaurav Jalan Location
- Bengaluru, KA, IN
Gaurav Jalan Work
- VP Engineering @ (May 2026 - Present)
- AVP Engineering @ (October 2023 - April 2026)
- Senior Director @ (April 2022 - October 2023)
- Transformation Coach (March 2024 - Present)
- CEO and Cofounder @ (May 2018 - April 2022)
- Blogger @ Siddhakarana (September 2010 - February 2019)
- Assistant Vice President, Engineering @ (February 2016 - May 2018)
- Member of Editorial Board @ EETimes India (July 2009 - December 2017)
- Past Chair @ (September 2016 - September 2017)
- General Chair @ (January 2015 - September 2016)
- Promotions Chair @ (August 2014 - December 2014)
- Director Engineering @ (April 2013 - January 2016)
- Senior Engineering Manager @ (January 2011 - March 2013)
- Engineering Manager @ (August 2009 - December 2011)
- Lead Engineer @ (August 2008 - August 2009)
- Senior Engineer @ (April 2007 - July 2008)
- Design Engineer @ (February 2005 - March 2007)
- Consultant @ (February 2003 - February 2005)
- Member Technical Staff @ (February 2003 - January 2005)
- Member Technical Staff @ (February 2002 - January 2003)
Gaurav Jalan Education
- SYMBIOSIS INTERNATIONAL UNIVERSITY
PGDBA (Marketing)
2004-2007 - Malaviya National Institute of Technology Jaipur
ME (VLSI)
2000-2002 - Chandrapur Engg. College, Chandrapur
BE (Electronics Engg)
1996-2000 - Vivekanand Kendra Vidyalaya
AISSCE (PCMBE)
1993-1995 - St. Paul School
AISSE (Science)
1980-1993
Gaurav Jalan Skills
- SoC
- ASIC
- IP
- Marketing Communications
- AHB
- Functional Verification
- VLSI
- SystemVerilog
- Verilog
- Specman
- NCSim
- C
- Semiconductors
- Low Power Design
- NC-Verilog
- AMBA AHB
- Low-power Design
- EDA
- Embedded Systems
- I2C
- Debugging
- Formal Verification
- Simulations
- JTAG
- FPGA
- USB
- ARM
- RF
- Wireless
- Integrated Circuit Design
- Processors
- Analog
- VHDL
- RTL design
- Application-Specific Integrated Circuits (ASIC)
- Very-Large-Scale Integration (VLSI)
- System on a Chip (SoC)
- Field-Programmable Gate Arrays (FPGA)
- Engineering
- Design
- Validation
- Field Programmable Gate Arrays Fpga
- Customer Service
- Very Large Scale Integration Vlsi
- Strategy
- Blogging
- Verification
- Data Validation
- Application Specific Integrated Circuits Asic
- System on a Chip Soc
- Sales
- Strategic Planning
- Nc Verilog
- Radio Frequency Rf
- ARM Architecture
- Internet Protocol Ip
- Wireless Technologies
- Joint Test Action Group Jtag
- Application Specific Integrated Circuits
- System on a Chip
- Very Large Scale Integration
- Field Programmable Gate Arrays
- Internet Protocol
- Joint Test Action Group
- Radio Frequency
Gaurav Jalan Summary
- Gaurav Jalan, based in Bengaluru, KA, IN, is currently a VP Engineering at Marvell Technology. Gaurav Jalan brings experience from previous roles at Marvell India, Self Employed and SpicaWorks. Gaurav Jalan holds a 2004 - 2007 PGDBA in Marketing @ SYMBIOSIS INTERNATIONAL UNIVERSITY. With a robust skill set that includes SoC, ASIC, IP, Marketing Communications, AHB and more. Gaurav Jalan has 2 emails and 1 mobile phone numbers on RocketReach.
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