William Binder Email & Phone Number

William Binder Skills

• EinsTimer/ChipBench EDA Tools
• Synopsys Synthesis Tools
• Mentor Graphics Simulation Tools
• VHDL
• Verilog
• Perl
• Tcl/TK
• C/C++
• PHP
• MySQL
• Cadence EDA Tools
• Python
• Java
• FPGA tools (Altera, Xilinx, ORCA)
• Static Timing Analysis
• ASIC
• Hardware Design
• Hardware Architecture
• Simulations
• TCL
• SoC
• VLSI
• Linux
• EDA
• Functional Verification
• Algorithms
• Logic Design
• Computer Architecture
• Timing Closure
• C++
• Low-power Design
• Debugging
• IC
• FPGA
• Processors
• Logic Synthesis
• Unix
• C
• Integration
• Semiconductors
• Microprocessors
• System Architecture
• RTL design
• High Performance Computing
• Timing
• Testing
• Software Engineering
• Physical Design
• Shell Scripting
• Asic Design
• Orca
• Hardware
• Business Analysis
• Xilinx
• Engineering
• Low Power Design
• Fpga Tools Altera
• Technical Leadership
• Design
• Project Management
• Fpga Tools