Viren Patel's Location

San Jose, CA, US

Viren Patel's Work

Viren Patel's Education

  • Dharmsinh Desai Institute of Technology

    Bachelor of Engineering (BE) (Electrical, Electronics and Communications Engineering)

    2008 - 2012
  • The H.B. Kapadiya new high school

    2006 - 2008

Viren Patel's Skills

  • ASIC
  • Physical Design
  • Static Timing Analysis
  • Physical Verification
  • TCL
  • Perl
  • Verilog
  • C
  • VLSI
  • RTL design

Viren Patel's Summary

Viren Patel, based in San Jose, CA, US, is currently a Sr Physical Design Engineer at NVIDIA, bringing experience from previous roles at eInfochips (An Arrow Company). Viren Patel holds a 2008 - 2012 Bachelor of Engineering (BE) in Electrical, Electronics and Communications Engineering @ Dharmsinh Desai Institute of Technology. With a robust skill set that includes ASIC, Physical Design, Static Timing Analysis, Physical Verification, TCL and more, Viren Patel contributes valuable insights to the industry. Viren Patel has 2 emails and 1 mobile phone number on RocketReach.

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