Vincent Fei Email & Phone Number
Principal Design Verification Engineer @ Astera Labs
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Vincent Fei Location
- Toronto, ON, CA
Vincent Fei Work
- 2025 -now Principal Design Verification Engineer @
- 2025 -2025 Principal Design Verification Engineer @
- 2022 -2025 SMTS Design Verification Engineer @
- 2020 -2022 MTS Verification engineer @
- 2015 -2020 ASIC Design Verification Engineer @
- 2014 -2015 ASIC Verification Engineer @
- 2013 -2014 Design Engineer @
- 2011 -2013 Logic Design Engineer @
- 2010 -2011 Verification Intern @ AMD
Vincent Fei Education
- Shanghai University
MS (Electronics Engineering)
2008-2011 - Shanghai University
BS (Electrical Automation)
2004-2008
Vincent Fei Skills
- Logic Design
- C/C++
- DDR3
- Ddr4
- DDR2
- Logic Synthesis
- Perl
- RTL design
- UVM
- PCIe
- ASIC
- AMBA AHB
- SATA
- Ahb
- VMM
- Verilog
- NCSim
- TCL
- Ethernet
- Memory Controllers
- FPGA
- SoC
- Wideio
- Lpddr2
- Timing Closure
- Python
- SystemVerilog
- Semiconductors
- Lpddr3
- Static Timing Analysis
- Amba
- AXI
- Pt
- Dc
- I2C
- DDR
Vincent Fei Summary
- Vincent Fei, based in Toronto, ON, CA, is currently a Principal Design Verification Engineer at Astera Labs. Vincent Fei brings experience from previous roles at Marvell Technology, AMD and Intel Corporation. Vincent Fei holds a 2008 - 2011 MS in Electronics Engineering @ Shanghai University. With a robust skill set that includes Logic Design, C/C++, DDR3, Ddr4, DDR2 and more. Vincent Fei has 3 emails and 2 mobile phone numbers on RocketReach.
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