Saravanan Kalinagasamy Email & Phone Number

Saravanan Kalinagasamy Email & Phone Number

Senior Director of Engineering, SoC Design Verification and Validation @ Aeva

Saravanan Kalinagasamy's Location

San Jose, CA, US

Saravanan Kalinagasamy's Work

  • Senior Director of Engineering, SoC Design Verification and Validation @ Aeva
  • Director of Engineering, SoC Functional and Performance Verification @ Xilinx
  • Senior Manager ASIC Design Verification @ SanDisk®

Saravanan Kalinagasamy's Education

  • University of Madras

Saravanan Kalinagasamy's Skills

  • Functional Verification
  • ASIC
  • Verilog
  • FPGA
  • SoC
  • SystemVerilog
  • VLSI
  • Debugging
  • RTL design
  • IC

Saravanan Kalinagasamy's Summary

Saravanan Kalinagasamy, based in San Jose, CA, US, is currently a Senior Director of Engineering, SoC Design Verification and Validation at Aeva, bringing experience from previous roles at Xilinx, SanDisk and Cortina Systems. Saravanan Kalinagasamy holds a University of Madras. With a robust skill set that includes Functional Verification, ASIC, Verilog, FPGA, SoC and more, Saravanan Kalinagasamy contributes valuable insights to the industry. Saravanan Kalinagasamy has 2 emails and 1 mobile phone number on RocketReach.

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