Vignesh Manoharan's Location

San Jose, CA, US

Vignesh Manoharan's Work

Vignesh Manoharan's Education

  • Vellore Institute of Technology

    M.Tech (VLSI Design)

    2005 - 2007
  • Anna University

    B.E (Electronics And Communication Engineering)

    2001 - 2005

Vignesh Manoharan's Skills

  • Apb
  • Debugging
  • System On A Chip Soc
  • Functional Verification
  • RTL design
  • I2S
  • UVM
  • Troubleshooting
  • ASIC
  • AMBA AHB

Vignesh Manoharan's Summary

Vignesh Manoharan, based in San Jose, CA, US, is currently a Verification Lead and Architect at Aeva, bringing experience from previous roles at Aeva, Inc, Intel Corporation, Broadcom and Atmel Corporation. Vignesh Manoharan holds a 2005 - 2007 M.Tech in VLSI Design @ Vellore Institute of Technology. With a robust skill set that includes Apb, Debugging, System On A Chip Soc, Functional Verification, RTL design and more, Vignesh Manoharan contributes valuable insights to the industry. Vignesh Manoharan has 4 emails and 1 mobile phone number on RocketReach.

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