Varada A Location
- Santa Clara, CA, US
Varada A Work
- 2022 -now Physical Design Engineer @
- 2020 -2022 Principal Product Engineer @
- 2018 -2020 Senior Physical Design Engineer @
- 2016 -2018 Module Lead Engineer @
- 2011 -2016 Graphics Hardware Engineer, Physical Design Team, Visual and Parallel computing Group @
- 2010 -2011 Graduate Technical Intern, Physical Design Team, Visual and Parallel computing Group @
Varada A Education
- Vellore Institute of Technology
Master of Technology - MTech (VLSI Design)
2009-2011 - Visvesvaraya Technological University
Bachelor of Engineering - BE (Electronics and Communications Engineering)
2005-2009
Varada A Skills
- ASIC
- Physical Design
- Static Timing Analysis
- Timing Closure
- Digital Circuit Design
- Logic Synthesis
- Scan Insertion
- Clock Tree Synthesis
- Place & Route
- Synopsys tools
- Synopsys Primetime
- ICC
- Physical Verification
- Signal Integrity
- Equivalence Checking
- Shell Scripting
- Tcl-Tk
- SoC
- C
- Verilog
- TCL
- EDA
- Semiconductors
- Very-Large-Scale Integration (VLSI)
- Tweaker ECO
- Calibre
Varada A Summary
- Varada A, based in Santa Clara, CA, US, is currently a Physical Design Engineer at Google. Varada A brings experience from previous roles at Cadence Design Systems, Synapse Design Inc. and Intel Corporation. Varada A holds a 2009 - 2011 Master of Technology - MTech in VLSI Design @ Vellore Institute of Technology. With a robust skill set that includes ASIC, Physical Design, Static Timing Analysis, Timing Closure, Digital Circuit Design and more. Varada A has 4 emails on RocketReach.
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Varada A
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