Tom Labonte Email & Phone Number
Senior NVLink Architect @ NVIDIA
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Tom Labonte Location
- Boston, MA, US
Tom Labonte Work
- Senior NVLink Architect @ (January 2025 - Present)
- Principal Engineer - Silicon Architecture @ (August 2023 - Present)
- Silicon Architect @ (October 2016 - December 2023)
- Configuration Architect @ (January 2015 - January 2017)
- Silicon Architecture Engineer @ (July 2001 - January 2015)
- Hardware Engineer @ (July 2000 - July 2001)
- Hardware Enginnering Intern @ (June 1998 - March 2000)
- Hardware Engineering Intern @ (November 1997 - March 1998)
Tom Labonte Education
- Rochester Institute of Technology
Bachelor of Science (BS) (Computer Engineering)
1995-2000
Tom Labonte Skills
- Application-Specific Integrated Circuits (ASIC)
- C++
- Cache Coherency
- Computer Architecture
- Congestion Management
- Continuous Integration
- Debugging
- Formal Specification
- Functional Verification
- Hardware Architecture
- Integration
- Integration Testing
- Logic Design
- Microarchitecture
- Microprocessors
- Network Architecture
- Network Design
- NoC
- Performance Modeling
- Perl
- Processors
- RTL design
- Semiconductors
- SoC
- SystemVerilog
- VLSI
- Validation
- Verilog
- Very-Large-Scale Integration (VLSI)
Tom Labonte Summary
- Tom Labonte, based in Boston, MA, US, is currently a Senior NVLink Architect at NVIDIA. Tom Labonte brings experience from previous roles at Samsung Semiconductor and Intel Corporation. Tom Labonte holds a 1995 - 2000 Bachelor of Science (BS) in Computer Engineering @ Rochester Institute of Technology. With a robust skill set that includes Application-Specific Integrated Circuits (ASIC), C++, Cache Coherency, Computer Architecture, Congestion Management and more. Tom Labonte has 3 emails and 1 mobile phone numbers on RocketReach.
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