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Thomas Jones Location
San Jose, CA, US
Thomas Jones Work
Digital Design Principle Engineer and Manager @ (January 2023 - Present)
Principal ASIC Design @ (May 2022 - December 2022)
Senior Principal Design Engineer @ (October 2018 - May 2022)
Principal Engineer @ NVXL Technology, Inc. (October 2017 - October 2018)
ASIC Design, Team Technical Lead @ (July 2016 - October 2017)
ASIC Designer @ (July 2005 - June 2016)
Designer @ TiMetra/Alcatel (January 2001 - January 2005)
Designer @ Sebring/PLX Technology (January 1998 - January 2001)
Designer @ (January 1994 - January 1998)
Designer @ Amdahl (January 1990 - January 1992)
Thomas Jones Education
Santa Clara University
MS (Computer Engineering)
1991-1997
Oregon Institute of Technology
Bachelor of Science (BS) (Computer Systems Engineering Technology)
1982-1987
Thomas Jones Skills
FPGA
ASIC
Verilog
SoC
Semiconductors
PCB design
Microcontrollers
Product Development
Start-ups
Embedded Systems
Perl
VHDL
C
C++
Linux
Java
Xilinx
TCL
Microprocessors
I2C
SPI
Modelsim
Xilinx ISE
Oscilloscope
Logic Analyzer
Function Generator
LSF
Tk
PLI
Synplify
DC
PT
Synopsys Formality
Cadence Conformal
Synopys Synplicity
Utopia
MII/GMII/SGMII
RTL Design
EDA
Altera
Architecture
Very-Large-Scale Integration (VLSI)
SystemVerilog
RTL Coding
Debugging
Hardware Architecture
Python (Programming Language)
Static Timing Analysis
Logic Synthesis
Thomas Jones Summary
Thomas Jones, based in San Jose, CA, US, is currently a Digital Design Principle Engineer and Manager at INNOPHASE. Thomas Jones brings experience from previous roles at Groq, Cadence Design Systems, NVXL Technology, Inc. and Enphase Energy. Thomas Jones holds a 1991 - 1997 MS in Computer Engineering @ Santa Clara University. With a robust skill set that includes FPGA, ASIC, Verilog, SoC, Semiconductors and more. Thomas Jones has 3 emails and 5 mobile phone numbers on RocketReach.
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