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Thomas Jones Location
San Jose, CA, US
Thomas Jones Work
2023 -now Digital Design Principle Engineer @
2022 -2022 Principal ASIC Design @
2018 -2022 Senior Principal Design Engineer @
2017 -2018 Principal Engineer @ NVXL Technology, Inc.
2016 -2017 ASIC Design, Team Technical Lead @
2005 -2016 ASIC Designer @
2001 -2005 Designer @ TiMetra/Alcatel
1998 -2001 Designer @ Sebring/PLX Technology
1994 -1998 Designer @
1990 -1992 Designer @ Amdahl
Thomas Jones Education
Santa Clara University
MS (Computer Engineering)
1991-1997
Oregon Institute of Technology
Bachelor of Science (BS) (Computer Systems Engineering Technology)
1982-1987
Thomas Jones Skills
FPGA
ASIC
Verilog
SoC
Semiconductors
PCB design
Microcontrollers
Product Development
Start-ups
Embedded Systems
Perl
VHDL
C
C++
Linux
Java
Xilinx
TCL
Microprocessors
I2C
SPI
Modelsim
Xilinx ISE
Oscilloscope
Logic Analyzer
Function Generator
LSF
Tk
PLI
Synplify
DC
PT
Synopsys Formality
Cadence Conformal
Synopys Synplicity
Utopia
MII/GMII/SGMII
RTL Design
EDA
Altera
Architecture
Very-Large-Scale Integration (VLSI)
SystemVerilog
RTL Coding
Debugging
Hardware Architecture
Python (Programming Language)
Static Timing Analysis
Logic Synthesis
Thomas Jones Summary
Thomas Jones, based in San Jose, CA, US, is currently a Digital Design Principle Engineer at INNOPHASE. Thomas Jones brings experience from previous roles at Groq, Cadence Design Systems, NVXL Technology, Inc. and Enphase Energy. Thomas Jones holds a 1991 - 1997 MS in Computer Engineering @ Santa Clara University. With a robust skill set that includes FPGA, ASIC, Verilog, SoC, Semiconductors and more. Thomas Jones has 3 emails and 5 mobile phone numbers on RocketReach.
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