Terry Magee Email & Phone Number
Senior Architect for Memory, IO, & Interconnect @ Intel Capital
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Terry Magee Location
- California, United States
Terry Magee Work
- Senior Architect for Memory, IO, & Interconnect @ (October 2018 - Present)
- Principal Engineer @ (August 2011 - October 2018)
- Principal Design Engineer @ (October 2008 - July 2011)
- Staff Design Engineer @ (July 2007 - October 2008)
- Staff Design Engineer @ (February 2004 - June 2007)
Terry Magee Education
- Trinity College, Dublin
Master of Science (Design)
1993-1995 - University College Dublin
(Engineering)
1989-1993
Terry Magee Skills
- Performance Modeling
- Silicon Design
- Silicon Architecture
- DDR5 LPDDR5 HBM
- Team Management
- Field-Programmable Gate Arrays (FPGA)
- Network-on-chip (NOC)
- ASIC
Terry Magee Summary
- Terry Magee, based in California, United States, is currently a Senior Architect for Memory, IO, & Interconnect at Intel Corporation. Terry Magee brings experience from previous roles at Xilinx, LSI Logic and Synopsys. Terry Magee holds a 1993 - 1995 Master of Science in Design @ Trinity College, Dublin. With a robust skill set that includes Performance Modeling, Silicon Design, Silicon Architecture, DDR5 LPDDR5 HBM, Team Management and more. Terry Magee has 1 emails and 2 mobile phone numbers on RocketReach.
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Terry Magee
Senior Architect for Memory, IO, & Interconnect
California, United States
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