Tejas Talati Email & Phone Number
Principal Engineer @ Marvell India
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Tejas Talati Location
- Cupertino, CA, US
Tejas Talati Work
- Principal Engineer @ (March 2015 - Present)
- Principal Engineer -IC Design @ (October 2014 - March 2015)
- PMTS @ (July 2011 - October 2014)
- Technical Leader @ (January 2004 - July 2011)
- Tech Champion @ (August 1997 - January 2004)
- Executive R and D @ Secure Meters Limited (January 1994 - January 1997)
Tejas Talati Education
- Birla Institute of Technology and Science, Pilani
Ms (Systems and Information Systems)
1995-1997 - Gujarat University
BE (Computer Engineering)
1989-1993
Tejas Talati Skills
- Vera
- Functional Verification
- SystemVerilog
- ASIC
- SoC
- Verilog
- NCSim
- VLSI
- PCIe
- UVM
- FPGA
- SystemC
- Embedded Systems
- Perl
- Debugging
- Testing
- Semiconductors
- C
- System on a Chip (SoC)
- Very-Large-Scale Integration (VLSI)
- System on a Chip Soc
- Application Specific Integrated Circuits Asic
- Very Large Scale Integration Vlsi
- System on a Chip
- Very Large Scale Integration
- Application Specific Integrated Circuits
Tejas Talati Summary
- Tejas Talati, based in Cupertino, CA, US, is currently a Principal Engineer at Marvell Technology. Tejas Talati brings experience from previous roles at Broadcom, Cortina Systems and eInfochips. Tejas Talati holds a 1995 - 1997 Ms in Systems and Information Systems @ Birla Institute of Technology and Science, Pilani. With a robust skill set that includes Vera, Functional Verification, SystemVerilog, ASIC, SoC and more. Tejas Talati has 2 emails and 2 mobile phone numbers on RocketReach.
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