Steven Loi Email & Phone Number
Staff FPGA Design Engineer @ Kateeva
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Steven Loi Location
- San Jose, CA, US
Steven Loi Work
- 2021 -now Staff FPGA Design Engineer @
- 2020 -2020 ASIC Design Engineer @
- 2017 -2020 Staff FPGA Design Engineer @
- 2013 -2017 Senior FPGA Hardware Engineer @
- 2007 -2013 Staff Engineer @
- 1999 -2007 ASIC Designer @
- 1996 -1999 ASIC Designer @ Silicon Magic
- 1995 -1996 ASIC Designer @ Cornerstone Imaging
- 1993 -1995 ASIC Designer @ Oki Semiconductor America
Steven Loi Education
- California State University-Sacramento
BS, EE
Steven Loi Skills
- FPGA
- Debugging
- RTOS
- SoC
- Embedded Systems
- ASIC
- Video Compression
- H.264
- Signal Processing
- Embedded Software
- Semiconductors
- Verilog
- ARM
- Device Drivers
- Firmware
- Management
- SQL
- Illustrator
- Engineering
- Graphic Design
Steven Loi Summary
- Steven Loi, based in San Jose, CA, US, is currently a Staff FPGA Design Engineer at Kateeva. Steven Loi brings experience from previous roles at Microsoft, Kateeva, EFI and Sigma Designs. Steven Loi holds a BS, EE @ California State University-Sacramento. With a robust skill set that includes FPGA, Debugging, RTOS, SoC, Embedded Systems and more. Steven Loi has 2 emails and 1 mobile phone numbers on RocketReach.
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