Steven Loi Email & Phone Number
Staff FPGA Design Engineer @ Kateeva
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Steven Loi Location
- San Jose, CA, US
Steven Loi Work
- Staff FPGA Design Engineer @ (January 2021 - Present)
- ASIC Design Engineer @ (March 2020 - December 2020)
- Staff FPGA Design Engineer @ (January 2017 - January 2020)
- Senior FPGA Hardware Engineer @ (April 2013 - January 2017)
- Staff Engineer @ (March 2007 - February 2013)
- ASIC Designer @ (November 1999 - March 2007)
- ASIC Designer @ Silicon Magic (November 1996 - November 1999)
- ASIC Designer @ Cornerstone Imaging (October 1995 - November 1996)
- ASIC Designer @ Oki Semiconductor America (August 1993 - October 1995)
Steven Loi Education
- California State University-Sacramento
BS (EE)
Steven Loi Skills
- FPGA
- Debugging
- RTOS
- SoC
- Embedded Systems
- ASIC
- Video Compression
- H.264
- Signal Processing
- Embedded Software
- Semiconductors
- Verilog
- ARM
- Device Drivers
- Firmware
- Management
- SQL
- Illustrator
- Engineering
- Graphic Design
Steven Loi Summary
- Steven Loi, based in San Jose, CA, US, is currently a Staff FPGA Design Engineer at Kateeva. Steven Loi brings experience from previous roles at Microsoft, Kateeva, EFI and Sigma Designs. Steven Loi holds a BS in EE @ California State University-Sacramento. With a robust skill set that includes FPGA, Debugging, RTOS, SoC, Embedded Systems and more. Steven Loi has 2 emails and 1 mobile phone numbers on RocketReach.
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