Stephen Barrett Email & Phone Number
Senior Principal Verification Engineer @ Jariet Technologies, Inc.
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Stephen Barrett Location
- Hollis, NH, US
Stephen Barrett Work
- Senior Principal Verification Engineer @ (January 2023 - Present)
- Verification Lead @ (June 2019 - January 2023)
- SOC Validation Engineer @ (June 2018 - June 2019)
- Senior Verification Engineer @ (June 2015 - March 2016)
- Staff ASIC Verification Engineer @ (July 2013 - June 2015)
- Senior Hardware Verification Engineer @ (March 2006 - July 2012)
- Test Engineer @ (January 2004 - January 2006)
- Test Engineer @ (January 2002 - January 2004)
- Hardware Verification Consultant @ (March 1999 - September 2001)
- Consultant @ (January 1999 - January 2000)
- Hardware Verification Consultant @ (January 1998 - January 1999)
- Hardware Design Engineer @ (January 1992 - January 1996)
- Engineer Assistant (Co-op) @ (January 1988 - January 1990)
- Intern @ Eastern Sound and Video (January 1984 - January 1986)
Stephen Barrett Education
- Worcester Polytechnic Institute 1993-1993
- University of Massachusetts at Lowell
BS (BS, Electrical Engineering with computer minor)
1985-1992
Stephen Barrett Skills
- Functional Verification
- SystemVerilog
- FPGA
- Debugging
- Verilog
- ASIC
- TCP/IP
- Hardware Architecture
- CVS
- Perl
- Linux
- PCIe
- Ethernet
- Testing
- Simulations
- Software Development
- Deep Packet Inspection
- Unix
- C++
- Embedded Software
- Hardware
- RTL design
- Shell Scripting
- Xilinx
- IC
- Internet Protocol Suite (TCP/IP)
- Application-Specific Integrated Circuits (ASIC)
- Git
- Universal Verification Methodology (UVM)
- Leadership
- Research
- Strategic Planning
- Universal Verification Methodology Uvm
- Field Programmable Gate Arrays Fpga
- Microsoft Excel
- Project Management
- PowerPoint
- Application Specific Integrated Circuits Asic
- Internet Protocol Suite Tcp/Ip
- Internet Protocol Suite
- Application Specific Integrated Circuits
- Universal Verification Methodology
- Field Programmable Gate Arrays
Stephen Barrett Summary
- Stephen Barrett, based in Hollis, NH, US, is currently a Senior Principal Verification Engineer at Jariet Technologies, Inc.. Stephen Barrett brings experience from previous roles at Panasonic USA, Intel Corporation, Violin Memory and Infinera. Stephen Barrett holds a 1993 - 1993 Worcester Polytechnic Institute. With a robust skill set that includes Functional Verification, SystemVerilog, FPGA, Debugging, Verilog and more. Stephen Barrett has 1 emails on RocketReach.
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