Sharad Arora's Location
San Jose, California, United States
Sharad Arora's Work
- Design Engineering Architect, DDR Design Ip @ Cadence Design Systems
- Senior Design Engineering Manager, DDR Design Ip @ Cadence Design Systems
- Lead Engineer, Timing and Physical Design @ Texas Instruments
- Design | Senior Design | Lead ] Engineer - Eda and Cad Methodology @ Texas Instruments
Sharad Arora's Education
- Faculty Of Management Studies And Research, Aligarh Muslim University
Bachelor of Technology (Computer Science)
1995 - 1999 - St Mary's Academy
Sharad Arora's Skills
- Static Timing Analysis
- Physical Design
- DDR
- IP
- SoC
- Timing Closure
- Logic Synthesis
- Timing Constraints
- Low Power Design
- Mentoring
Sharad Arora's Summary
Sharad Arora, based in San Jose, California, United States, is currently a Design Engineering Architect, DDR Design Ip at Cadence Design Systems, bringing experience from previous roles at Cadence Design Systems and Texas Instruments. Sharad Arora holds a 1995 - 1999 Bachelor of Technology in Computer Science @ Faculty Of Management Studies And Research, Aligarh Muslim University. With a robust skill set that includes Static Timing Analysis, Physical Design, DDR, IP, SoC and more, Sharad Arora contributes valuable insights to the industry. Sharad Arora has 1 email on RocketReach.
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