Sanjive Agarwala Email & Phone Number
Corporate Vice President and General Manager, IP Group @ Cadence Design Systems
Sanjive Agarwala's Location
San Jose, CA, US
Sanjive Agarwala's Work
- Corporate Vice President and General Manager, IP Group @ Cadence Design Systems
- Corporate Vice President, Tensilica IP Group @ Cadence Design Systems
- Senior Director of WW Silicon Development and TI Fellow, Processors @ Texas Instruments
- TI Fellow and DSPS Engineering Manager @ Texas Instruments
- TI Fellow and DSPS Engineering Manager @ Texas Instruments
Sanjive Agarwala's Education
- Southern Methodist University
Masters (Computer Science)
1987 - 1989 - Punjab Engineering College
Bachelor (Electronics & Electrical Communication)
1980 - 1984
Sanjive Agarwala's Skills
- Digital Signal Processors
- Semiconductors
- EDA
- ASIC
- Embedded Systems
- ARM
- SoC
- Engineering Management
- Debugging
- Verilog
Sanjive Agarwala's Summary
Sanjive Agarwala, based in San Jose, CA, US, is currently a Corporate Vice President and General Manager, IP Group at Cadence Design Systems, bringing experience from previous roles at Cadence Design Systems and Texas Instruments, Dallas, TX. Sanjive Agarwala holds a 1987 - 1989 Masters in Computer Science @ Southern Methodist University. With a robust skill set that includes Digital Signal Processors, Semiconductors, EDA, ASIC, Embedded Systems and more, Sanjive Agarwala contributes valuable insights to the industry. Sanjive Agarwala has 2 emails and 1 mobile phone number on RocketReach.
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