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Sarin Thomas Location
Sunnyvale, CA, US
Sarin Thomas Work
Hardware Engineer @ (January 2017 - Present)
Principal Engineer @ (May 2001 - January 2017)
Member Of Technical Staff @ (January 1999 - January 2001)
Hardware Design Engineer @ (January 1998 - January 1999)
Member Of Technical Staff @ (January 1995 - January 1998)
Sarin Thomas Education
Stanford University
MS (Electrical Engineering)
National Institute of Technology Calicut
BS (Electronics and Communication Engg)
Sarin Thomas Skills
ASIC
RTL Verification
SystemVerilog
Verilog
Perl
SoC
RTL design
Sarin Thomas Summary
Sarin Thomas, based in Sunnyvale, CA, US, is currently a Hardware Engineer at Google. Sarin Thomas brings experience from previous roles at Juniper Networks, HAL Computer Systems, First Virtual Communications (FVC.com / CMOS Soft Inc.) and HCL Technologies. Sarin Thomas holds a MS in Electrical Engineering @ Stanford University. With a robust skill set that includes ASIC, RTL Verification, SystemVerilog, Verilog, Perl and more. Sarin Thomas has 5 emails and 1 mobile phone numbers on RocketReach.
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