Saravanan S Email
Principal Engineer - AI Memory Systems Architect, JEDEC Representative @ Intel Corporation
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Saravanan S Location
- United States
Saravanan S Work
- 2021 - now Principal Engineer - AI Memory Systems Architect, JEDEC Representative @
- 2019 - 2021 Systems Hardware Architect @
- 2014 - now JEDEC Representative - Intel and IBM @
- 2015 - 2019 Senior Research and Development, JEDEC Representative @
- 2010 - 2015 Advisory Research Engineer @
- 2006 - 2010 Staff and Senior Staff Research Engineer @
- 2003 - 2006 Technical Lead - Hardware @
- 2000 - 2003 Research Engineer (Scientist) @
- 1999 - 2000 Systems Engineer @
Saravanan S Education
- Birla Institute of Technology and Science, Pilani
Doctor of Philosophy - PhD (Future Memory Technologies Reliability Improvements)
2014 - 2022 - Birla Institute of Technology and Science, Pilani
Master of Science - MS (Software Systems)
- Bharathidasan University
Bachelor of Engineering - BE (Electrical, Electronics and Communications Engineering)
Saravanan S Summary
- Saravanan S, based in United States, is currently a Principal Engineer - AI Memory Systems Architect, JEDEC Representative at Intel Corporation. Saravanan S brings experience from previous roles at Intel Corporation, JEDEC and IBM. Saravanan S holds a 2014 - 2022 Doctor of Philosophy - PhD in Future Memory Technologies Reliability Improvements @ Birla Institute of Technology and Science, Pilani. Saravanan S has 4 emails on RocketReach.
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