Sai Mandala Email
DFT Engineer @ BITSILICA
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Sai Mandala Location
- Hyderabad, IN
Sai Mandala Work
- DFT Engineer @ (October 2019 - Present)
Sai Mandala Education
- Auroras Technological and Research Institute (ATRI)
Bachelor of Engineering - BE (Electronics and Communication Engineering)
2014-2019
Sai Mandala Skills
- Synopsys Formality
- Coverage Analysis
- EDA
- EDT
- Verilog
- scan compression
- DFT
- DFT Compiler
- Scan Insertion
- Automatic Test Pattern Generation (ATPG)
- Application-Specific Integrated Circuits (ASIC)
- Very-Large-Scale Integration (VLSI)
- Python (Programming Language)
- Tcl-Tk
- sign-off
- sta
- Synopsys tools
- Design Compiler
- Genus
- Scikit-RF
Sai Mandala Summary
- Sai Mandala, based in Hyderabad, IN, is currently a DFT Engineer at BITSILICA. Sai Mandala holds a 2014 - 2019 Bachelor of Engineering - BE in Electronics and Communication Engineering @ Auroras Technological and Research Institute (ATRI). With a robust skill set that includes Synopsys Formality, Coverage Analysis, EDA, EDT, Verilog and more. Sai Mandala has 2 emails on RocketReach.
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