Ryan Zhu Email & Phone Number
Principal DFX Methodology Engineer @ NVIDIA
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Ryan Zhu Location
- California, United States
Ryan Zhu Work
- Principal DFX Methodology Engineer @ (March 2026 - Present)
- Senior DFX Methodology Engineer @ (November 2022 - March 2026)
- Senior DFT Engineer @ (August 2018 - November 2022)
- Staff Design Engineer @ (July 2014 - July 2018)
- Senior Design Engineer @ (April 2013 - July 2014)
- Senior ASIC Design Engineer @ (October 2008 - April 2013)
Ryan Zhu Education
- University of Rochester
MS ( Electrical Engineering )
2005-2007 - East China Normal University
BS ( Electrical Engineering )
Ryan Zhu Skills
- SoC
- ASIC
- DFT
- Semiconductors
- FPGA
- Algorithms
- ARM Architecture
- Debugging
- Testing
- System on a Chip (SoC)
- Field-Programmable Gate Arrays (FPGA)
- python
- Verilog
- Embedded Systems
- C
- Java
- Static Timing Analysis
- Integrated Circuit Design
- Logic Synthesis
- Timing Closure
- SystemVerilog
- Functional Verification
- Python (Programming Language)
- System on a Chip
- Field Programmable Gate Arrays
Ryan Zhu Summary
- Ryan Zhu, based in California, United States, is currently a Principal DFX Methodology Engineer at NVIDIA. Ryan Zhu brings experience from previous roles at NVIDIA, Marvell Semiconductor and Altera. Ryan Zhu holds a 2005 - 2007 MS in Electrical Engineering @ University of Rochester . With a robust skill set that includes SoC, ASIC, DFT, Semiconductors, FPGA and more. Ryan Zhu has 4 emails and 1 mobile phone numbers on RocketReach.
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