Robert Padilla Email & Phone Number
Sr Staff ATE Engineer @ NVIDIA
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Robert Padilla Location
- San Jose, CA, US
Robert Padilla Work
- Sr Staff ATE Engineer @ (February 2003 - Present)
- Member Of Technical Staff @ (June 2001 - February 2003)
- Sr Staff Engineer @ C-Cube Microsystems (January 1995 - June 2001)
- Test Engineering Manager @ C-Cube Microsystems (January 1995 - January 2001)
- Test Engineering Manager @ (April 1990 - June 1995)
Robert Padilla Education
- University of California, Berkeley
BSEE/CS (computer systems design and technology)
- University of California, Berkeley
BSEE & CS (Electrical and Electronics Engineering)
Robert Padilla Skills
- ASIC
- Debugging
- Processors
- VLSI
- PCB design
- Testing
- Mixed Signal
- IC
- C++
- Semiconductors
- Product Engineering
- Test Engineering
- ATPG
- Software Development
- CMOS
- SoC
- DFT
- Perl
- Microprocessors
- Verilog
- Hardware
- BIST
- JTAG
- Hardware Architecture
- EDA
- Residential Remodeling
- Custom Construction
Robert Padilla Summary
- Robert Padilla, based in San Jose, CA, US, is currently a Sr Staff ATE Engineer at Nvidia. Robert Padilla brings experience from previous roles at Transmeta, C-Cube Microsystems and Cypress Semiconductor. Robert Padilla holds a BSEE/CS in computer systems design and technology @ University of California, Berkeley. With a robust skill set that includes ASIC, Debugging, Processors, VLSI, PCB design and more. Robert Padilla has 1 emails and 1 mobile phone numbers on RocketReach.
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